Design of submicron PMOSFETs for DRAM array applications

Design of submicron PMOSFETs for DRAM array applications

A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the 'end-of-life' magnitude of subthreshold off-current at...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: El-Kareh, B., Abadeer, W.W., Tonti, W.R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Acceleration
Boron
CMOS technology
Degradation
Hot carrier effects
Hot carriers
MOSFETs
Random access memory
Stress
Threshold voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 384
container_issue
container_start_page 379
container_title
container_volume
creator El-Kareh, B.
Abadeer, W.W.
Tonti, W.R.
description A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the 'end-of-life' magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 mu m. The minimum channel length of buried channels must be increased by approximately=0.25 mu m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of approximately=30%.< >
doi_str_mv 10.1109/IEDM.1991.235374
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_235374</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>235374</ieee_id><sourcerecordid>235374</sourcerecordid><originalsourceid>FETCH-LOGICAL-i89t-529d2104c95b2ef65ecff07a4e410f52db8c8ebebfa67e9fd10b8ef2bb477933</originalsourceid><addsrcrecordid>eNotj7tOwzAUQC0eEmlhR0z-gYR7_YjtsWoKVGpUBAxslZ3YyKhNIrsM_XuEynSmc6RDyD1ChQjmcb1q2gqNwYpxyZW4IAVDWZeA6vOSzEBp4MAEl1ekAKx5iQb1DZnl_A3AlDSyILrxOX4NdAw0_7hD7NI40Nd2-_60-sg0jIk2b4uW2pTsidpp2sfOHuM45FtyHew--7t_zsmfsnwpN9vn9XKxKaM2x1Iy0zME0RnpmA-19F0IoKzwAiFI1jvdae-8C7ZW3oQewWkfmHNCKcP5nDycq9F7v5tSPNh02p13-S8VaEbk</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Design of submicron PMOSFETs for DRAM array applications</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>El-Kareh, B. ; Abadeer, W.W. ; Tonti, W.R.</creator><creatorcontrib>El-Kareh, B. ; Abadeer, W.W. ; Tonti, W.R.</creatorcontrib><description>A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the 'end-of-life' magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 mu m. The minimum channel length of buried channels must be increased by approximately=0.25 mu m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of approximately=30%.&lt; &gt;</description><identifier>ISSN: 0163-1918</identifier><identifier>ISBN: 0780302435</identifier><identifier>ISBN: 9780780302433</identifier><identifier>EISSN: 2156-017X</identifier><identifier>DOI: 10.1109/IEDM.1991.235374</identifier><language>eng</language><publisher>IEEE</publisher><subject>Acceleration ; Boron ; CMOS technology ; Degradation ; Hot carrier effects ; Hot carriers ; MOSFETs ; Random access memory ; Stress ; Threshold voltage</subject><ispartof>International Electron Devices Meeting 1991 [Technical Digest], 1991, p.379-384</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/235374$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/235374$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>El-Kareh, B.</creatorcontrib><creatorcontrib>Abadeer, W.W.</creatorcontrib><creatorcontrib>Tonti, W.R.</creatorcontrib><title>Design of submicron PMOSFETs for DRAM array applications</title><title>International Electron Devices Meeting 1991 [Technical Digest]</title><addtitle>IEDM</addtitle><description>A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the 'end-of-life' magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 mu m. The minimum channel length of buried channels must be increased by approximately=0.25 mu m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of approximately=30%.&lt; &gt;</description><subject>Acceleration</subject><subject>Boron</subject><subject>CMOS technology</subject><subject>Degradation</subject><subject>Hot carrier effects</subject><subject>Hot carriers</subject><subject>MOSFETs</subject><subject>Random access memory</subject><subject>Stress</subject><subject>Threshold voltage</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>0780302435</isbn><isbn>9780780302433</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj7tOwzAUQC0eEmlhR0z-gYR7_YjtsWoKVGpUBAxslZ3YyKhNIrsM_XuEynSmc6RDyD1ChQjmcb1q2gqNwYpxyZW4IAVDWZeA6vOSzEBp4MAEl1ekAKx5iQb1DZnl_A3AlDSyILrxOX4NdAw0_7hD7NI40Nd2-_60-sg0jIk2b4uW2pTsidpp2sfOHuM45FtyHew--7t_zsmfsnwpN9vn9XKxKaM2x1Iy0zME0RnpmA-19F0IoKzwAiFI1jvdae-8C7ZW3oQewWkfmHNCKcP5nDycq9F7v5tSPNh02p13-S8VaEbk</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>El-Kareh, B.</creator><creator>Abadeer, W.W.</creator><creator>Tonti, W.R.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>Design of submicron PMOSFETs for DRAM array applications</title><author>El-Kareh, B. ; Abadeer, W.W. ; Tonti, W.R.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i89t-529d2104c95b2ef65ecff07a4e410f52db8c8ebebfa67e9fd10b8ef2bb477933</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Acceleration</topic><topic>Boron</topic><topic>CMOS technology</topic><topic>Degradation</topic><topic>Hot carrier effects</topic><topic>Hot carriers</topic><topic>MOSFETs</topic><topic>Random access memory</topic><topic>Stress</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>El-Kareh, B.</creatorcontrib><creatorcontrib>Abadeer, W.W.</creatorcontrib><creatorcontrib>Tonti, W.R.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>El-Kareh, B.</au><au>Abadeer, W.W.</au><au>Tonti, W.R.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of submicron PMOSFETs for DRAM array applications</atitle><btitle>International Electron Devices Meeting 1991 [Technical Digest]</btitle><stitle>IEDM</stitle><date>1991</date><risdate>1991</risdate><spage>379</spage><epage>384</epage><pages>379-384</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>0780302435</isbn><isbn>9780780302433</isbn><abstract>A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the 'end-of-life' magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 mu m. The minimum channel length of buried channels must be increased by approximately=0.25 mu m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of approximately=30%.&lt; &gt;</abstract><pub>IEEE</pub><doi>10.1109/IEDM.1991.235374</doi><tpages>6</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0163-1918
ispartof International Electron Devices Meeting 1991 [Technical Digest], 1991, p.379-384
issn 0163-1918
2156-017X
language eng
recordid cdi_ieee_primary_235374
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Acceleration
Boron
CMOS technology
Degradation
Hot carrier effects
Hot carriers
MOSFETs
Random access memory
Stress
Threshold voltage
title Design of submicron PMOSFETs for DRAM array applications
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-11T12%3A54%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Design%20of%20submicron%20PMOSFETs%20for%20DRAM%20array%20applications&rft.btitle=International%20Electron%20Devices%20Meeting%201991%20%5BTechnical%20Digest%5D&rft.au=El-Kareh,%20B.&rft.date=1991&rft.spage=379&rft.epage=384&rft.pages=379-384&rft.issn=0163-1918&rft.eissn=2156-017X&rft.isbn=0780302435&rft.isbn_list=9780780302433&rft_id=info:doi/10.1109/IEDM.1991.235374&rft_dat=%3Cieee_6IE%3E235374%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=235374&rfr_iscdi=true