Design of submicron PMOSFETs for DRAM array applications

A comparison is made between surface-channel P/sup +/ polysilicon gate and buried-channel N/sup +/ polysilicon gate PMOSFETs used as switching devices in DRAM arrays in a 3.3 V CMOS technology. The criterion for this comparison is the 'end-of-life' magnitude of subthreshold off-current at zero gate-to-source voltage, projected from accelerated hot-carrier stress. Shifts in off-current depend on changes in threshold voltage and subthreshold slope. The minimum channel length which satisfies the lifetime criterion of 100% shift in off-current for surface channels is 0.3 mu m. The minimum channel length of buried channels must be increased by approximately=0.25 mu m over that of surface channels to meet the same lifetime criterion. This results in a reduction in drain current of approximately=30%.< >