Folding an array of transistors and contacts
The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding,...
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| container_end_page | 2972 vol.6 |
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| container_start_page | 2969 |
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| container_volume | 6 |
| creator | Hu, T.C. Moerder, K.E. Morgenthaler, J.D. |
| description | The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding, and is equivalent to channel routing. As a part of this algorithm, a graph labeling procedure is described which generalized the well-known topological sorting algorithm for directed acyclic graphs.< > |
| doi_str_mv | 10.1109/ISCAS.1992.230698 |
| format | Conference Proceeding |
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They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding, and is equivalent to channel routing. As a part of this algorithm, a graph labeling procedure is described which generalized the well-known topological sorting algorithm for directed acyclic graphs.< ></description><identifier>ISBN: 9780780305939</identifier><identifier>ISBN: 0780305930</identifier><identifier>DOI: 10.1109/ISCAS.1992.230698</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuits ; Computer science ; Design engineering ; Labeling ; Logic functions ; Programmable logic arrays ; Routing ; Sorting ; Very large scale integration ; Wire</subject><ispartof>1992 IEEE International Symposium on Circuits and Systems (ISCAS), 1992, Vol.6, p.2969-2972 vol.6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/230698$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/230698$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hu, T.C.</creatorcontrib><creatorcontrib>Moerder, K.E.</creatorcontrib><creatorcontrib>Morgenthaler, J.D.</creatorcontrib><title>Folding an array of transistors and contacts</title><title>1992 IEEE International Symposium on Circuits and Systems (ISCAS)</title><addtitle>ISCAS</addtitle><description>The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. 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As a part of this algorithm, a graph labeling procedure is described which generalized the well-known topological sorting algorithm for directed acyclic graphs.< ></description><subject>Circuits</subject><subject>Computer science</subject><subject>Design engineering</subject><subject>Labeling</subject><subject>Logic functions</subject><subject>Programmable logic arrays</subject><subject>Routing</subject><subject>Sorting</subject><subject>Very large scale integration</subject><subject>Wire</subject><isbn>9780780305939</isbn><isbn>0780305930</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1992</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01LAzEYhAMiKHV_gJ7yA9w1H2-SzbEsVguFHtqey7v5kEjdlSSX_nsX6jAw8BxmGEKeOes4Z_ZtexjWh45bKzohmbb9HWms6dliyZSV9oE0pXyzRaCYFfKRvG7mi0_TF8WJYs54pXOkNeNUUqlzLgv31M1TRVfLE7mPeCmh-c8VOW3ej8Nnu9t_bIf1rk3cQG0RnBeaMZQclhHlfOxZ0CIE63tvjIYRRlRRAWhnevACNfAQzTiGEIWQK_Jy600hhPNvTj-Yr-fbJfkH-sNBGA</recordid><startdate>1992</startdate><enddate>1992</enddate><creator>Hu, T.C.</creator><creator>Moerder, K.E.</creator><creator>Morgenthaler, J.D.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1992</creationdate><title>Folding an array of transistors and contacts</title><author>Hu, T.C. ; Moerder, K.E. ; Morgenthaler, J.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i174t-a4cd2600a3149235cdf80e62ee9d8d7764b4ba5f5446c784d2a641ef7bbeef223</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Circuits</topic><topic>Computer science</topic><topic>Design engineering</topic><topic>Labeling</topic><topic>Logic functions</topic><topic>Programmable logic arrays</topic><topic>Routing</topic><topic>Sorting</topic><topic>Very large scale integration</topic><topic>Wire</topic><toplevel>online_resources</toplevel><creatorcontrib>Hu, T.C.</creatorcontrib><creatorcontrib>Moerder, K.E.</creatorcontrib><creatorcontrib>Morgenthaler, J.D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hu, T.C.</au><au>Moerder, K.E.</au><au>Morgenthaler, J.D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Folding an array of transistors and contacts</atitle><btitle>1992 IEEE International Symposium on Circuits and Systems (ISCAS)</btitle><stitle>ISCAS</stitle><date>1992</date><risdate>1992</risdate><volume>6</volume><spage>2969</spage><epage>2972 vol.6</epage><pages>2969-2972 vol.6</pages><isbn>9780780305939</isbn><isbn>0780305930</isbn><abstract>The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding, and is equivalent to channel routing. As a part of this algorithm, a graph labeling procedure is described which generalized the well-known topological sorting algorithm for directed acyclic graphs.< ></abstract><pub>IEEE</pub><doi>10.1109/ISCAS.1992.230698</doi></addata></record> |
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| identifier | ISBN: 9780780305939 |
| ispartof | 1992 IEEE International Symposium on Circuits and Systems (ISCAS), 1992, Vol.6, p.2969-2972 vol.6 |
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| language | eng |
| recordid | cdi_ieee_primary_230698 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Computer science Design engineering Labeling Logic functions Programmable logic arrays Routing Sorting Very large scale integration Wire |
| title | Folding an array of transistors and contacts |
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