Folding an array of transistors and contacts

Folding an array of transistors and contacts

The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding,...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Hu, T.C., Moerder, K.E., Morgenthaler, J.D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Computer science
Design engineering
Labeling
Logic functions
Programmable logic arrays
Routing
Sorting
Very large scale integration
Wire
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Beschreibung
Zusammenfassung:The authors present a unified graph model for representing various layout and routing problems in VLSI design, such as programmable logic array (PLA) folding, gate matrix layout, and channel routing. They introduce an algorithm for folding a Weinberger array. This is a generalization of PLA folding, and is equivalent to channel routing. As a part of this algorithm, a graph labeling procedure is described which generalized the well-known topological sorting algorithm for directed acyclic graphs.< >
DOI:10.1109/ISCAS.1992.230698