A combined Reed-Solomon encoder and syndrome generator with small hardware complexity

In most applications of a Reed-Solomon codec (coder/decoder) data are either being transmitted or being received where either the encoder or the decoder is active, while the other is idle. The idea presented is to show how the encoder can be transformed such that its implementation can make use of existing decoder circuitry, requiring only little additional hardware dedicated to the encoder. In CMOS design examples which were studied the encoder hardware savings amounted to more than 90%. The architecture can easily be programmed for different error correction powers.< >