Design and implementation of the data-path of a 32-bit RISC microprocessor:HRISCII

Describes the design and the implementation of the data-path of a 32-bit RISC microprocessor called HRISCII. This unit was designed to operate with a 20 MHz clock rate, has been implemented in a 2 micron, two layers metal, one polysilicon CMOS process. It contains about 16 000 transistors and occupi...

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Bibliographische Detailangaben
Hauptverfasser:	El-haffaf, Y.I., Bouaraoua, A., Amari, A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Circuits Clocks CMOS process Computer aided instruction Computer architecture Microelectronics Microprocessors Multiplexing Reduced instruction set computing Registers
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Beschreibung
Zusammenfassung:	Describes the design and the implementation of the data-path of a 32-bit RISC microprocessor called HRISCII. This unit was designed to operate with a 20 MHz clock rate, has been implemented in a 2 micron, two layers metal, one polysilicon CMOS process. It contains about 16 000 transistors and occupies an area of 20 mm/sup 2/.< >
DOI:	10.1109/EUASIC.1992.228043