Evaluation of Futurebus+ for a GMMP multiprocessor

One of the most popular approaches for increasing computer performance is parallel computations using specialized hardware. Clearly, the authors would like to use standardized technology wherever possible in such multiprocessors, in order to minimize the number of unique components that must be (re)designed for each generation of the machine. This paper presents the result of a modelling study that was undertaken to estimate the performance achievable by an implementation of the virtual port memory multiprocessor architecture using the Futurebus+ backplane bus structure. Discrete event simulation and analytical queueing network models concur that peak performance occurs, for typical workloads, at approximately 30 processors on the bus.< >