Area-efficient architectures for the Viterbi algorithm II. Applications

Area-efficient architectures for the Viterbi algorithm II. Applications

In part I the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm were established. Area-efficient architectures for practical codes are presented here to illustrate the design procedures and demonstrate the favourable area-time tradeoff results. Three ex...

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Veröffentlicht in:IEEE transactions on communications 1993-05, Vol.41 (5), p.802-807
Hauptverfasser: Shung, C.B., Lin, H.-D., Cypher, R., Siegel, P.H., Thapar, H.K.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Coding, codes
Communications Society
Convolutional codes
Decoding
Exact sciences and technology
Information, signal and communications theory
Modulation coding
Partial response channels
Pipelines
Scheduling
Signal and communications theory
Signal processing
Telecommunications and information theory
Very large scale integration
Viterbi algorithm
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Beschreibung
Zusammenfassung:In part I the theoretical foundations of a new class of area-efficient architectures for the Viterbi algorithm were established. Area-efficient architectures for practical codes are presented here to illustrate the design procedures and demonstrate the favourable area-time tradeoff results. Three examples from convolutional codes, matched-spectral-null (MSN) trellis codes, and Ungerboeck codes are presented. The application of the area-efficient techniques to codes with a very large number of states, codes with time-varying trellises, and a programmable Viterbi decoder is discussed.< >
ISSN:0090-6778
1558-0857
DOI:10.1109/26.225495