VLSI design of an 8-bit fixed point CORDIC processor with extended operation set

An architecture of a DSP fixed point, pipelined processor is presented. It provides a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications. The processor architecture is based on the CORDIC and CCM algorithms and it is fully parallel and pipelined. An 8-bit fixed point chip has been designed using the VENUS-S semicustom design system in CMOS 1.5 mu m technology.< >