A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus

A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus

A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded...

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Hauptverfasser: Matsumiya, M., Kawashima, S., Sakata, M., Miyabo, T., Koga, T., Itabashi, K., Mizutani, K., Ema, T., Toyoda, K., Yabu, T., Shimada, H., Suzuki, N., Ookura, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Current measurement
Delay effects
Energy consumption
Lithography
Power dissipation
Random access memory
Semiconductor device measurement
Thin film transistors
Voltage
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Zusammenfassung:A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded sense amplifier and current sense amplifier. The waveforms of the address input and the data output lines at room temperature with a 3-V supply are shown. The access time is typically 15 ns, with an active current consumption of 55 mA at 3.0 V and 30 MHz.< >
DOI:10.1109/ISSCC.1992.200488