Built-in self parallel testing for functional faults in megabit RAMs

A test algorithm and design scheme are proposed for a built-in self testing technique for functional faults in semiconductor random access memories. The test algorithm detects stuck-at and pattern sensitive faults over a neighborhood of nine cells. An n-bit memory is composed of p square sub-arrays,...

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Hauptverfasser: Hur, Y.D., Cho, H.M., Lee, J.H., Cho, S.B.
Format: Tagungsbericht
Sprache:eng
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Zusammenfassung:A test algorithm and design scheme are proposed for a built-in self testing technique for functional faults in semiconductor random access memories. The test algorithm detects stuck-at and pattern sensitive faults over a neighborhood of nine cells. An n-bit memory is composed of p square sub-arrays, and this algorithm takes 2310 (n/p)/sup 1/2/ testing cycles. The row address generator, test pattern generator, parallel pattern loader, and parallel data comparator are added to the conventional RAM circuits for the built-in self testing function.< >
DOI:10.1109/ISCAS.1991.176201