A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip

A Leakage Management System Based on Clock Gating Infrastructure for a 65-nm Digital Base-Band Modem Chip

In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage...

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Hauptverfasser: Ko, U., Raibaut, C., Ciroux, J., Fournet-Fayard, C., Lachese, J.L., Domerego, O., Bouetel, L., Ben-Amar, F., Ball, M., Rosal, J., Culp, N., Piacibello, F., Vaccani, J., Hollingsworth, R., Menezes, V., Clinton, M., Thiruvengadam, S., Gururajarao, S., Chau, M., Lagerquist, R., Er Rachidi, A., Scott, D., Mair, H., Royannez, P., Jumel, F.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Control systems
Energy management
Leakage current
Modems
Power system management
Random access memory
Switches
Voltage
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Beschreibung
Zusammenfassung:In this paper we present a leakage management system which takes advantage of the existing clock gating infrastructure. This methodology avoids both RTL and software changes, at the block and chip level. We illustrate this approach with a 65-nm digital base band modem while achieving standby leakage in the 100-muA range and overall 1200times leakage reduction including process, circuit and system optimization
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2006.1705386