Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

Paired FinFET Charge Trap Flash Memory for Vertical High Density Storage

A new type of memory, paired FinFET charge trap memory is reported. It consists of two split silicon fins and insulator between them. Two channels are formed on the outer surface of silicon so doubled integration density can be achieved. We successfully fabricated paired FinFET SONOS devices. It sho...

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Hauptverfasser: Kim, S., Kim, W., Hyun, J., Byun, S., Koo, J., Lee, J., Cho, K., Lim, S., Park, J., Yoo, I.-K., Lee, C.-H., Park, D., Park, Y.
Format: Tagungsbericht
Sprache:eng ; jpn
Schlagworte:
Circuits
Electron traps
FinFETs
Flash memory
Insulation
Research and development
Scalability
Silicon
SONOS devices
Testing
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Beschreibung
Zusammenfassung:A new type of memory, paired FinFET charge trap memory is reported. It consists of two split silicon fins and insulator between them. Two channels are formed on the outer surface of silicon so doubled integration density can be achieved. We successfully fabricated paired FinFET SONOS devices. It shows good program and erase characteristics. Independent programming on each storage nodes is demonstrated. The circuit configuration for NAND flash application is also proposed
ISSN:0743-1562
DOI:10.1109/VLSIT.2006.1705228