A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS

A 1GS/s 11b Time-Interleaved ADC in 0.13/spl mu/m CMOS

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB peak SNDR, consumes 250mW power, and occupies 3.5mm 2 area

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Bibliographische Detailangaben
Hauptverfasser: Gupta, S., Choi, M., Inerfield, M., Jingbo Wang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bandwidth
Circuits
Clocks
Error correction
Linearity
Sampling methods
Signal processing
Signal sampling
Switches
Timing
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Beschreibung
Zusammenfassung:A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is scalable to high sampling rates is presented. This 1GS/S 11b ADC has 55dB peak SNDR, consumes 250mW power, and occupies 3.5mm 2 area
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2006.1696299