A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% to 70% duty-cycle input clock operating from 20 to...

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Hauptverfasser: Tokunaga, Y., Sakiyama, S., Dosho, S., Yasuyuki Doi, Hattori, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Active filters
Charge pumps
Circuits
Clocks
Delay
Jitter
Partial discharges
Timing
Virtual colonoscopy
Voltage control
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Beschreibung
Zusammenfassung:A duty-cycle-correcting false-lock-free DLL for DDR interface is proposed. A fully balanced charge-pump equalizes the charge and discharge pulses of the phase detector to reduce update noise. The DLL achieved 49% to 51% duty-cycle output from a 30% to 70% duty-cycle input clock operating from 20 to 300MHz, consumes 9mW from a 2 to 4V supply, and occupies 0.03mm 2 in a 0.30μm CMOS process
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2006.1696176