A Power-Efficient High-Throughput 32-Thread SPARC Processor

A Power-Efficient High-Throughput 32-Thread SPARC Processor

The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity. The design combines eight 4-threaded 64b cores, a high-bandwidth crossbar, a shared 3MB L2 Cache and four DDR2 DRAM interfaces. The...

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Bibliographische Detailangaben
Hauptverfasser: Leon, A.S., Jinuk Luke Shin, Tam, K.W., Bryg, W., Schumacher, F., Kongetira, P., Weisner, D., Strong, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
Delay
Frequency
Pipelines
Registers
Semiconductor device measurement
Sun
Temperature measurement
Throughput
Yarn
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Beschreibung
Zusammenfassung:The first generation of Niagara SPARC processors implements a power-efficient multi-threading architecture to achieve high throughput with minimum hardware complexity. The design combines eight 4-threaded 64b cores, a high-bandwidth crossbar, a shared 3MB L2 Cache and four DDR2 DRAM interfaces. The 90nm 378mm 2 die consumes 63W at 1.2GHz. Memory design techniques to support the high bandwidth are also discussed
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2006.1696060