CMOS voltage-mode analog multiplier

CMOS voltage-mode analog multiplier

This paper proposes a CMOS voltage-mode four-quadrant analog multiplier. It is based on a pair of diode-connected MOS transistor that is biased with a constant current source, and a CMOS voltage difference circuit. Simulation results shows that the linear range is plusmn400 mV with the linearity err...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Boonchu, B., Surakampontorn, W.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit simulation
CMOS technology
Communications technology
Diodes
Harmonic distortion
Linearity
MOSFETs
Threshold voltage
Transconductance
Variable structure systems
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Beschreibung
Zusammenfassung:This paper proposes a CMOS voltage-mode four-quadrant analog multiplier. It is based on a pair of diode-connected MOS transistor that is biased with a constant current source, and a CMOS voltage difference circuit. Simulation results shows that the linear range is plusmn400 mV with the linearity error of 0.8% and the harmonic distortion of 0.62%. The minus;3dB bandwidth of 30MHz is achieved at the power consumption of 1.26mW
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1693003