A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q 2 random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors