Performance and routability improvements for routability-driven FPGA routers

Performance and routability improvements for routability-driven FPGA routers

Routing FPGAs (Verma, 1999) is a challenging problem because of the relative scarcity of routing resources represented in wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals (McMurchie, 1995). T...

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Bibliographische Detailangaben
Hauptverfasser: Boshra, S.M., Abbas, H.M., Darwish, A.M., Talkhan, I.E.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit synthesis
Field programmable gate arrays
Hardware design languages
Logic arrays
Logic circuits
Logic programming
Pins
Routing
Software algorithms
Wiring
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Beschreibung
Zusammenfassung:Routing FPGAs (Verma, 1999) is a challenging problem because of the relative scarcity of routing resources represented in wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals (McMurchie, 1995). This paper presents some enhancements to improve both the performance and routability of the routability-driven routing using the versatile place and route VPR routing tool (Betz, 1999). Testing MCNC benchmarks has shown the efficiency of these enhancements
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2006.1692641