Memory Interference in Synchronous Multiprocessor Systems

Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introdu...

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Veröffentlicht in:	IEEE Trans. Comput.; (United States) 1982-11, Vol.C-31 (11), p.1116-1121
Hauptverfasser:	Yen, D W L, Patel, J H, Davidson, E S
Format:	Artikel
Sprache:	eng
Schlagworte:	990200 - Mathematics & Computers Analytical models ARCHITECTURE ARRAY PROCESSORS GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE MATHEMATICAL MODELS memory bandwidth MEMORY DEVICES memory interference multiprocessor systems performance evaluation QUEUES SYNCHRONIZATION
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Beschreibung
Zusammenfassung:	Synchronous N-processor systems with M shared memories are considered. Memory interference is modeled for processor request rates between 0 and 1 per memory cycle. Two probability-based models and one queueing-based model are summarized from prior literature. A new steady-state flow model is introduced. This steady-state model is most accurate overall. The queueing model is somewhat more accurate when request rate is near 1, and M and N are large. Accuracy is established with respect to probabilistic simulation. Additional related models are described.
ISSN:	0018-9340 1557-9956
DOI:	10.1109/TC.1982.1675928