A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations

A scalable Stacked Gate NOR/NAND Flash Technology compatible with high-k and metal gates for sub 45nm generations

In this paper a scalable stacked gate technology with self-aligned floating gate (FG) is presented. It can be used for both NOR and NAND flash architectures. By introducing high-k materials for the interpoly dielectric (IPD) a planar structure can be used, which allows a much denser structure. It is...

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Hauptverfasser: De Vos, J., Haspeslagh, L., Demand, M., Devriendt, K., Wellekens, D., Beckx, S., Houdt, J.V.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Character generation
Controllability
Etching
Filling
High K dielectric materials
High-K gate dielectrics
Inorganic materials
Nonvolatile memory
Slurries
Tin
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Beschreibung
Zusammenfassung:In this paper a scalable stacked gate technology with self-aligned floating gate (FG) is presented. It can be used for both NOR and NAND flash architectures. By introducing high-k materials for the interpoly dielectric (IPD) a planar structure can be used, which allows a much denser structure. It is also shown that the planar structure of the memory cell facilitates the introduction of metal gates. The successful integration of a 110nm stacked gate transistor with high-k IPD and TiN metal gate is illustrated
ISSN:2381-3555
2691-0462
DOI:10.1109/ICICDT.2006.220783