A 200-MHz 64-b dual-issue CMOS microprocessor

A 200-MHz 64-b dual-issue CMOS microprocessor

A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75- mu m CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm*13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruc...

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Veröffentlicht in:IEEE journal of solid-state circuits 1992-11, Vol.27 (11), p.1555-1567
Hauptverfasser: Dobberpuhl, D.W., Witek, R.T., Allmon, R., Anglin, R., Bertucci, D., Britton, S., Chao, L., Conrad, R.A., Dever, D.E., Gieseke, B., Hassoun, S.M.N., Hoeppner, G.W., Kuchler, K., Ladd, M., Leary, B.M., Madden, L., McLellan, E.J., Meyer, D.R., Montanaro, J., Priore, D.A., Rajagopalan, V., Samudrala, S., Santhanam, S.
Format: Artikel
Sprache:eng
Schlagworte:
Chaos
Clocks
CMOS process
CMOS technology
Microprocessors
Pins
Power dissipation
Registers
Very large scale integration
Wires
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Zusammenfassung:A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75- mu m CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm*13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.165336