A +7.9dBm IIP3 LNA for CDMA2000 in a 90nm digital CMOS process

A +7.9dBm IIP3 LNA for CDMA2000 in a 90nm digital CMOS process

A highly linear low noise amplifier (LNA) has been implemented in a standard digital 90nm CMOS process. At 880MHz the amplifier provides a forward power gain (S21) of 14.5dB with a supply voltage of 1.4V and a current consumption of 8.3mA. The noise figure was measured to be 1.0dB and the input thir...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: Griffith, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS process
Frequency
Intermodulation distortion
Jamming
Low-noise amplifiers
Microwave amplifiers
Mobile handsets
Noise figure
Peak to average power ratio
Switches
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Beschreibung
Zusammenfassung:A highly linear low noise amplifier (LNA) has been implemented in a standard digital 90nm CMOS process. At 880MHz the amplifier provides a forward power gain (S21) of 14.5dB with a supply voltage of 1.4V and a current consumption of 8.3mA. The noise figure was measured to be 1.0dB and the input third order intercept point (IP3) is +7.9dBm. Two lower gain modes have also been implemented; one with a lower transconductance gain stage, and one with a bypass switch. These performance parameters make the amplifier suited for the CDMA2000 cellular standard
ISSN:1529-2517
2375-0995
DOI:10.1109/RFIC.2006.1651201