Memory chip for 24-port global register file
The design of 256*32 bit 24-port global register file is discussed. An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental...
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| creator | Maly, W. Patyra, M. Primatic, A. Raghavan, V. Storey, T. Wolfe, A. |
| description | The design of 256*32 bit 24-port global register file is discussed. An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental, CMOS implementation of this SRAM chip are reported in detail.< > |
| doi_str_mv | 10.1109/CICC.1991.164130 |
| format | Conference Proceeding |
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An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental, CMOS implementation of this SRAM chip are reported in detail.< ></description><identifier>ISBN: 9780780300156</identifier><identifier>ISBN: 0780300157</identifier><identifier>DOI: 10.1109/CICC.1991.164130</identifier><language>eng</language><publisher>IEEE</publisher><subject>CMOS technology ; Concurrent computing ; Data processing ; Delay ; Measurement ; Parallel processing ; Program processors ; Random access memory ; Registers ; SRAM chips</subject><ispartof>Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, p.15.5/1-15.5/4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/164130$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,4050,4051,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/164130$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Maly, W.</creatorcontrib><creatorcontrib>Patyra, M.</creatorcontrib><creatorcontrib>Primatic, A.</creatorcontrib><creatorcontrib>Raghavan, V.</creatorcontrib><creatorcontrib>Storey, T.</creatorcontrib><creatorcontrib>Wolfe, A.</creatorcontrib><title>Memory chip for 24-port global register file</title><title>Proceedings of the IEEE 1991 Custom Integrated Circuits Conference</title><addtitle>CICC</addtitle><description>The design of 256*32 bit 24-port global register file is discussed. An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. 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An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental, CMOS implementation of this SRAM chip are reported in detail.< ></abstract><pub>IEEE</pub><doi>10.1109/CICC.1991.164130</doi></addata></record> |
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| identifier | ISBN: 9780780300156 |
| ispartof | Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, p.15.5/1-15.5/4 |
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| language | eng |
| recordid | cdi_ieee_primary_164130 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS technology Concurrent computing Data processing Delay Measurement Parallel processing Program processors Random access memory Registers SRAM chips |
| title | Memory chip for 24-port global register file |
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