Memory chip for 24-port global register file

Memory chip for 24-port global register file

The design of 256*32 bit 24-port global register file is discussed. An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental...

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Bibliographische Detailangaben
Hauptverfasser: Maly, W., Patyra, M., Primatic, A., Raghavan, V., Storey, T., Wolfe, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
CMOS technology
Concurrent computing
Data processing
Delay
Measurement
Parallel processing
Program processors
Random access memory
Registers
SRAM chips
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Zusammenfassung:The design of 256*32 bit 24-port global register file is discussed. An eight-read- and eight-write-port SRAM (static random-access memory) chip is proposed as a building block of such a global register file. Design trade-offs and performance measurements obtained from a 65 K+transistor, experimental, CMOS implementation of this SRAM chip are reported in detail.< >
DOI:10.1109/CICC.1991.164130