An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link

The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Benz, C., Gowan, M., Springer, K.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 7.1/4
container_issue
container_start_page 7.1/1
container_title
container_volume
creator Benz, C.
Gowan, M.
Springer, K.
description The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at ECL compatible levels (other portions of the chips operate at 31.25 MHz). IEEE P1149.1 is used for boundary and internal scan. The coding, block diagrams of the chips, CMOS/ECL transceivers, and results are discussed.< >
doi_str_mv 10.1109/CICC.1991.164059
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_164059</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>164059</ieee_id><sourcerecordid>164059</sourcerecordid><originalsourceid>FETCH-LOGICAL-i87t-4413255d5aa085fa4eef5bfd65ab7710bd24127e0653b427260662d305be44803</originalsourceid><addsrcrecordid>eNotT01LxDAUDIigrL2Lp_yBdt9L8tL2uBStCwte9r4kzYtE13ZJe_HfW6jDwHwcBkaIZ4QKEdp9d-y6CtsWK7QGqL0TRVs3sFIDINkHUczzF6wgapD0o-gPo-Scp1wOU848LGn8lDwOU-As3Rhk4M3Hac0SZe_Tsp9lTH4tp9uSBnlN4_eTuI_uOnPxrztxfns9d-_l6aM_dodTmZp6KY1BrYgCOQcNRWeYI_kYLDlf1wg-KIOqZrCkvVG1smCtChrIszHri5142WYTM19uOf24_HvZzuo_IWFIBw</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Benz, C. ; Gowan, M. ; Springer, K.</creator><creatorcontrib>Benz, C. ; Gowan, M. ; Springer, K.</creatorcontrib><description>The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at ECL compatible levels (other portions of the chips operate at 31.25 MHz). IEEE P1149.1 is used for boundary and internal scan. The coding, block diagrams of the chips, CMOS/ECL transceivers, and results are discussed.&lt; &gt;</description><identifier>ISBN: 9780780300156</identifier><identifier>ISBN: 0780300157</identifier><identifier>DOI: 10.1109/CICC.1991.164059</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Decoding ; Elasticity ; Encoding ; Error correction ; Forward error correction ; Logic ; Multiplexing ; Optical buffering ; Optical fibers</subject><ispartof>Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, p.7.1/1-7.1/4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/164059$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,4036,4037,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/164059$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Benz, C.</creatorcontrib><creatorcontrib>Gowan, M.</creatorcontrib><creatorcontrib>Springer, K.</creatorcontrib><title>An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link</title><title>Proceedings of the IEEE 1991 Custom Integrated Circuits Conference</title><addtitle>CICC</addtitle><description>The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at ECL compatible levels (other portions of the chips operate at 31.25 MHz). IEEE P1149.1 is used for boundary and internal scan. The coding, block diagrams of the chips, CMOS/ECL transceivers, and results are discussed.&lt; &gt;</description><subject>Clocks</subject><subject>Decoding</subject><subject>Elasticity</subject><subject>Encoding</subject><subject>Error correction</subject><subject>Forward error correction</subject><subject>Logic</subject><subject>Multiplexing</subject><subject>Optical buffering</subject><subject>Optical fibers</subject><isbn>9780780300156</isbn><isbn>0780300157</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1991</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotT01LxDAUDIigrL2Lp_yBdt9L8tL2uBStCwte9r4kzYtE13ZJe_HfW6jDwHwcBkaIZ4QKEdp9d-y6CtsWK7QGqL0TRVs3sFIDINkHUczzF6wgapD0o-gPo-Scp1wOU848LGn8lDwOU-As3Rhk4M3Hac0SZe_Tsp9lTH4tp9uSBnlN4_eTuI_uOnPxrztxfns9d-_l6aM_dodTmZp6KY1BrYgCOQcNRWeYI_kYLDlf1wg-KIOqZrCkvVG1smCtChrIszHri5142WYTM19uOf24_HvZzuo_IWFIBw</recordid><startdate>1991</startdate><enddate>1991</enddate><creator>Benz, C.</creator><creator>Gowan, M.</creator><creator>Springer, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1991</creationdate><title>An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link</title><author>Benz, C. ; Gowan, M. ; Springer, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i87t-4413255d5aa085fa4eef5bfd65ab7710bd24127e0653b427260662d305be44803</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1991</creationdate><topic>Clocks</topic><topic>Decoding</topic><topic>Elasticity</topic><topic>Encoding</topic><topic>Error correction</topic><topic>Forward error correction</topic><topic>Logic</topic><topic>Multiplexing</topic><topic>Optical buffering</topic><topic>Optical fibers</topic><toplevel>online_resources</toplevel><creatorcontrib>Benz, C.</creatorcontrib><creatorcontrib>Gowan, M.</creatorcontrib><creatorcontrib>Springer, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Benz, C.</au><au>Gowan, M.</au><au>Springer, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link</atitle><btitle>Proceedings of the IEEE 1991 Custom Integrated Circuits Conference</btitle><stitle>CICC</stitle><date>1991</date><risdate>1991</risdate><spage>7.1/1</spage><epage>7.1/4</epage><pages>7.1/1-7.1/4</pages><isbn>9780780300156</isbn><isbn>0780300157</isbn><abstract>The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at ECL compatible levels (other portions of the chips operate at 31.25 MHz). IEEE P1149.1 is used for boundary and internal scan. The coding, block diagrams of the chips, CMOS/ECL transceivers, and results are discussed.&lt; &gt;</abstract><pub>IEEE</pub><doi>10.1109/CICC.1991.164059</doi></addata></record>
fulltext fulltext_linktorsrc
identifier ISBN: 9780780300156
ispartof Proceedings of the IEEE 1991 Custom Integrated Circuits Conference, 1991, p.7.1/1-7.1/4
issn
language eng
recordid cdi_ieee_primary_164059
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Clocks
Decoding
Elasticity
Encoding
Error correction
Forward error correction
Logic
Multiplexing
Optical buffering
Optical fibers
title An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T02%3A06%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=An%20error-correcting%20encoder%20and%20decoder%20for%20a%201%20Gbit/s%20fiber%20optic%20link&rft.btitle=Proceedings%20of%20the%20IEEE%201991%20Custom%20Integrated%20Circuits%20Conference&rft.au=Benz,%20C.&rft.date=1991&rft.spage=7.1/1&rft.epage=7.1/4&rft.pages=7.1/1-7.1/4&rft.isbn=9780780300156&rft.isbn_list=0780300157&rft_id=info:doi/10.1109/CICC.1991.164059&rft_dat=%3Cieee_6IE%3E164059%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=164059&rfr_iscdi=true