An error-correcting encoder and decoder for a 1 Gbit/s fiber optic link

The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at...

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Hauptverfasser:	Benz, C., Gowan, M., Springer, K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Decoding Elasticity Encoding Error correction Forward error correction Logic Multiplexing Optical buffering Optical fibers
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Zusammenfassung:	The authors describe two chips, an encoder and a decoder for a 1-Gb/s fiber-optic data link, which implement 8-b/10-b coding, error detection and correction, framing and elasticity buffering. Fabricated in a 1.5- mu m CMOS process, the chips have a high-speed interface that operates at 93.75 MHz at ECL compatible levels (other portions of the chips operate at 31.25 MHz). IEEE P1149.1 is used for boundary and internal scan. The coding, block diagrams of the chips, CMOS/ECL transceivers, and results are discussed.< >
DOI:	10.1109/CICC.1991.164059