The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in a Technology for Volume Semiconductor Manufacturing

The Grand Pareto: A Methodology for Identifying and Quantifying Yield Detractors in a Technology for Volume Semiconductor Manufacturing

A method of communicating a unified pareto, we call "Grand Pareto", for technology-wide defects that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical f...

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Bibliographische Detailangaben
Hauptverfasser: Berndlmaier, Z., Winslow, J., Desineni, R., Blauberg, A., Chu, B.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Failure analysis
Inspection
Logic testing
Manufacturing
Microprocessors
Production facilities
Profitability
Semiconductor device manufacture
Vehicles
Yield estimation
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Beschreibung
Zusammenfassung:A method of communicating a unified pareto, we call "Grand Pareto", for technology-wide defects that limit the profitability of a fabrication facility is presented. The Grand Pareto leverages multiple defect detection and isolation techniques in conjunction with state-of-the-art physical failure analysis to create a single message for the process community to drive the yield improvement efforts. The methodology has been successfully deployed at IBM where it has been assisting in identifying key yield detractors for several high-end microprocessors in volume production
ISSN:1078-8743
2376-6697
DOI:10.1109/ASMC.2006.1638792