New Aspects in HDL's Performance Evaluation

New Aspects in HDL's Performance Evaluation

New aspects in hardware description language's (HDL) performance evaluation such as object-orientation, system-level modeling, analog and mixed-signal modeling, software description and verification capabilities are analyzed in this paper. Features of mainstream HDLs and verification languages...

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Hauptverfasser: Andelkovic, B., Litovski, V., Zerbe, V.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Counting circuits
Frequency domain analysis
Hardware description languages
Hardware design languages
hardware verification languages
Java
Object oriented modeling
Performance analysis
Power system modeling
Software performance
System-on-a-chip
SystemC
SystemVerilog
VHDL-AMS
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Beschreibung
Zusammenfassung:New aspects in hardware description language's (HDL) performance evaluation such as object-orientation, system-level modeling, analog and mixed-signal modeling, software description and verification capabilities are analyzed in this paper. Features of mainstream HDLs and verification languages VHDL-AMS, Java, SystemC, AleC++, MLDesigner, Open Vera, the e language, PSL and SystemVerilog are compared in the context of these aspects
DOI:10.1109/EURCON.2005.1629974