A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software

A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software

This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated ana...

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Hauptverfasser: Karthikeyan, M., Fox, S., Cote, W., Yeric, G., Hall, M., Garcia, J., Mitchell, B., Wolf, E., Agarwal, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application software
Automatic testing
Character generation
Circuit testing
Cost function
Electronics industry
Optical arrays
Software testing
Topology
Vehicles
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Beschreibung
Zusammenfassung:This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65nm random and systematic yield. This infrastructure consists of a 4Mb addressable-array test circuit with > 8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.
ISSN:1071-9032
2158-1029
DOI:10.1109/ICMTS.2006.1614284