A Wide-Band Digital Phase-Locked Looop

A high speed digital phase-locked loop (DPLL) is designed using 0.18..m CMOS process, using a 3.3V power supply. It operates in the frequency range 55MHz - 1.43GHz. A (PFD) phase frequency detector has a zero dead-zone by including delay elements in the Reset path. The current source used in the charge pump makes it insensitive to supply variations and provides ripple-free control voltage for the VCO (voltage controlled oscillator), which provides low jitter and no overshoot in locking transients. A high damping factor of 1.65 is used to keep the PLL stable. Simulation results using CADENCE tools are provided to verify the desired performance.