A 14-bit 20-msamples/s pipelined A/D converter with digital background calibration

This paper describes a 14-bit 20MSPS switched-capacitor pipelined ADC that employs digital background calibration to correct capacitor mismatch. The calibration concept is amenable to implementation in SOC because it is digital in nature. The calibration concept is demonstrated offline though in principle it can be included on-chip. The calibration can also be performed periodically, thus is inherently able to track the operating conditions of the device. Implementation is in a complimentary bipolar process. The prototype exhibits typical INL of /spl plusmn/ 2.0 LSB, DNL of /spl plusmn/ 0.4 LSB, SNR of 73 dB and SFDR of 85 dB with a 2 MHz input signal. Analog power is about 500 mW with 5 V supply.