Design of an extremely high performance counter mode AES reconfigurable processor

Design of an extremely high performance counter mode AES reconfigurable processor

In this paper, we presented our implementation of a counter mode AES processor based on the Xilinx Virtex2 FPGA platform. We have studied different techniques to implement the AES rijndael algorithm in reconfigurable hardware and choose the proper method to further optimize the structure of the ciph...

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Bibliographische Detailangaben
Hauptverfasser: Yongzhi Fu, Lin Hao, Xuejie Zhang, Rujin Yang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application specific integrated circuits
Counting circuits
Cryptography
Field programmable gate arrays
Hardware
Optimization methods
Output feedback
Security
Software performance
Throughput
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Beschreibung
Zusammenfassung:In this paper, we presented our implementation of a counter mode AES processor based on the Xilinx Virtex2 FPGA platform. We have studied different techniques to implement the AES rijndael algorithm in reconfigurable hardware and choose the proper method to further optimize the structure of the cipher. This result in a clock frequency of 212.5 mHz and translate to throughput of 27.1 Gb/s, the highest throughput that have ever reported. We also, in this paper, compared the operation modes of AES, their security and efficiency.
DOI:10.1109/ICESS.2005.43