Implementation of a semi-formal verification for embedded systems

Implementation of a semi-formal verification for embedded systems

In the era of billion-transistor design, it is critical to establish effective verification technologies from the system level, all the way down to the implementations. This paper presents a PNPM simulation based verification methodology for equivalence checking between different abstraction levels...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Zhu Yun, Li Xi, Zhao Siyang, Gong Yuchang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computational modeling
Computer architecture
Computer science
Design methodology
Digital signal processors
Embedded system
Formal verification
Microprocessors
State-space methods
Testing
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Beschreibung
Zusammenfassung:In the era of billion-transistor design, it is critical to establish effective verification technologies from the system level, all the way down to the implementations. This paper presents a PNPM simulation based verification methodology for equivalence checking between different abstraction levels and property verification at different abstraction levels. How to implement it with coverage-aware input biasing is elaborated.
DOI:10.1109/ICESS.2005.63