Energy-Efficient Thread-Level Speculation

Energy-Efficient Thread-Level Speculation

Chip multiprocessors with thread-level speculation have become the subject of intense research, this article refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism

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Bibliographische Detailangaben
Veröffentlicht in:IEEE MICRO 2006-01, Vol.26 (1), p.80-91
Hauptverfasser: Renau, J., Strauss, K., Ceze, L., Liu, W., Sarangi, S.R., Tuck, J., Torrellas, J.
Format: Artikel
Sprache:eng
Schlagworte:
chip multiprocessors
Chips (electronics)
Design optimization
Energy consumption
Energy efficiency
Engines
Hardware
Integrated circuits
Microarchitecture
Microprocessors
Multiprocessor
Out of order
out-of-order task spawning
Parallel processing
Process design
Runtime
Tasks
Thread-level speculation
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Beschreibung
Zusammenfassung:Chip multiprocessors with thread-level speculation have become the subject of intense research, this article refutes the claim that such a design is necessarily too energy inefficient. In addition, it proposes out-of-order task spawning to exploit more sources of speculative task-level parallelism
ISSN:0272-1732
1937-4143
DOI:10.1109/MM.2006.11