Dual-mode high-speed low-energy binary addition

Sparse tree adders are a common choice for the implementation of high performance binary addition. However, for constant supply voltage they have constant energy consumption regardless of the operating frequency. This paper presents a dual-mode sparse tree adder that offers a low-speed low-energy mode. This is achieved by disabling the prefix tree in the low-speed mode. Simulation results using extracted mask layouts show a reduction in energy consumption in the low-speed mode by a factor of 3.6 in static CMOS and a factor of 2.3 in domino logic