Hitachi-PA/50, SH series microcontroller

Design methodologies for Hitachi's RISC microprocessors and microcontrollers are discussed. One of the processors is a high-end PA-RISCTM. The others, the PA/50 and the SH series microcontroller, are low power and low cost processors. Low cost processors require small chip sizeand short design time. To shorten the architecture level design time, we have developed a RT-level behavior simulation tool based on C language. And to reduce the total design time, we use a gate-level synthesis program from the behavior model description. This approach resulted in the low power 42 MIPS/W PA-RISCTM processor (the PA/50, which run at a 33 MHz clock rate) being completed within 15months. Another approach to minimizing chip size while maintaining high performance is to reduce the design turnaround time by using microcode instead of direct wired logic design. We wrote 480-word microcodes equivalent to a 5.8K transistor logic. After assigning the control stages for the microcode fields, we used an in-house logic synthesis and optimized for performance and chip size. The CPU core of the SH series microcontroller occupies only 8 mm2 including CPU core and multiplier circuit. The processor reaches 16 MIPS at 20 MHz. It took 17 man-months to realize a minimum 8 mm2 chip. The total control logic consists of 27 thousand transistors.