Performance optimization using exact sensitization

A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay t. We describe a new delay optimization procedure that optimizes only sensitizable paths greater than t. Unlike previous methods that use topological ana...

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Hauptverfasser:	Saldanha, Alexander, Harkness, Heather, McGeer, Patrick C., Brayton, Robert K., Sangiovanni-Vincentelli, Alberto L.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Acceleration Boolean functions Circuit synthesis Circuit topology Delay Hardware > Electronic design automation > Logic synthesis > Circuit optimization Hardware > Integrated circuits > Logic circuits > Combinational circuits Hardware > Integrated circuits > Logic circuits > Sequential circuits Length measurement Logic circuits Optimization methods Sequential circuits Timing
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