Performance optimization using exact sensitization

A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay t. We describe a new delay optimization procedure that optimizes only sensitizable paths greater than t. Unlike previous methods that use topological analysis only, this method accounts for both functional and topological interactions in the circuit. Comprehensive experimental results comparing the proposed technique to a state-of-the-art performance optimization procedure are presented for combinational and sequential logic circuits.