Minimal redundancy, low power bus coding

Minimal redundancy, low power bus coding

A new approach to low redundancy coding for reducing power dissipation in parallel on-chip, deep sub-micron buses is presented. It is shown that the new approach allows lower power dissipation than previous solutions in the given model, yielding reductions of 24% to 41% compared to uncoded transmiss...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Lindkvist, T., Lofvenberg, J.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Coupling circuits
Energy consumption
Frequency
Jacobian matrices
Parasitic capacitance
Power dissipation
Semiconductor device modeling
Throughput
Ultra large scale integration
Wires
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Beschreibung
Zusammenfassung:A new approach to low redundancy coding for reducing power dissipation in parallel on-chip, deep sub-micron buses is presented. It is shown that the new approach allows lower power dissipation than previous solutions in the given model, yielding reductions of 24% to 41% compared to uncoded transmission for the considered bus widths. Finally some important open problems are given.
DOI:10.1109/NORCHP.2005.1597043