Mapping the DVB physical layer onto SDR-enabled protocol processor hardware

We present the design and implementation of configurable protocol processor hardware modules for SDR applications. We approach the problem by mapping digital television functionality onto our existing TTA protocol processor architecture. The implemented hardware modules include symbol, bit and convolutional deinterleavers, depuncturer and demapper. The hardware was synthesized using 0.18 /spl mu/m technology and verified with VHDL simulations. The resulting processor area was 2.2 mm/sup 2/ which is almost three times the area we have previously obtained for a complex network layer processor with identical data transport capacity.