Device simulation study of silicon p-channel FinFETs

This paper examines the performance and scaling characteristics of p-channel silicon FinFETs (pFinFETs) using three dimensional device modeling based on a drift-diffusion model. A commercial numerical device simulator was employed to investigate the device's short channel effects down to a channel length of 20 nm. The results show that the pFinFET provides good scaling characteristics with the subthreshold slope increasing from 66 mV/dec to 76 mV/dec and the drain induced barrier lowering from 17 m V/V to 80 m V/V as the gate length decreases from 80 to 20 nm's. Subsequently, the performance of the pFinFET at high frequencies was examined for a gate length of 50 nm with promising results. Peak values of the cutoff frequency f/sub T/ and maximum frequency of oscillation f/sub max/ of 53 GHz and 211 GHz, respectively, were obtained as the gate bias was swept. These preliminary results indicate the potential for high peiformance pFINFETs.