Yet Another Silicon Compiler

In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface logic. A novel technique for lay...

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Hauptverfasser: Krekelberg, D.E., Sobelman, G.E., Jhon, C.S.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:In this paper, we describe the YASC high-level silicon compiler which synthesizes compact chip layouts from hierarchical behavioral descriptions. A logic synthesis procedure generates sets of Boolean equations, including multi-phase clocks and any necessary interface logic. A novel technique for layout generation yields cells whose densities approach hand-crafted designs. Two-layer metal NMOS and CMOS technologies are supported, with flexible design rules. In addition to layout synthesis, logic, schematic and graph diagrams are generated directly from a powerful internal data base. The compiler, which runs under the UNIX operating sysrem, including a menu-driven multi-windowing user environment.
ISSN:0738-100X
DOI:10.1109/DAC.1985.1585932