CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system

CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system

This paper presents solutions to realize a high-speed, high-precision CMOS timing generator for a 4.266-Gbps memory test system. In order to realize such a timing generator, we developed a 1.066-GHz CMOS timing generator circuit using a high-speed digital delay locked loop circuit and a high-speed,...

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Bibliographische Detailangaben
Hauptverfasser: Suda, M., Yamamoto, K., Okayasu, T., Kantake, S., Sudou, S., Watanabe, D.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Clocks
CMOS process
Costs
Delay effects
Frequency
Logic circuits
Power generation
Signal generators
System testing
Timing jitter
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Beschreibung
Zusammenfassung:This paper presents solutions to realize a high-speed, high-precision CMOS timing generator for a 4.266-Gbps memory test system. In order to realize such a timing generator, we developed a 1.066-GHz CMOS timing generator circuit using a high-speed digital delay locked loop circuit and a high-speed, low-INL fine delay circuit. Consequently, we realized a timing generator with 1/20 the size, 4/9 the power, and frac12 the timing error (INL = 8 ps, total jitter =16.8 ps) compared with a conventional timing generator fabricated by the same CMOS process
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2005.1584050