Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain

This paper presents a new modular SOC test architecture that uses an improved single TAM daisy-chain for scan test access to embedded modules. The architecture by definition guarantees that the total SOC test time is close to the lower bound. To make third party IP cores to fit the architecture, IP...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Waayers, T., Morren, R., Grandi, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Buildings Laboratories Logic testing Manufacturing Merging Robustness Semiconductor device testing Silicon System testing System-on-a-chip
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