Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain

Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain

This paper presents a new modular SOC test architecture that uses an improved single TAM daisy-chain for scan test access to embedded modules. The architecture by definition guarantees that the total SOC test time is close to the lower bound. To make third party IP cores to fit the architecture, IP...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Waayers, T., Morren, R., Grandi, R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Buildings
Laboratories
Logic testing
Manufacturing
Merging
Robustness
Semiconductor device testing
Silicon
System testing
System-on-a-chip
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents a new modular SOC test architecture that uses an improved single TAM daisy-chain for scan test access to embedded modules. The architecture by definition guarantees that the total SOC test time is close to the lower bound. To make third party IP cores to fit the architecture, IP with test infrastructure 'on-demand' is introduced. An area-efficient bypass implementation for our IEEE std. 1500 compliant test wrapper is presented and results from a single TAM daisy-chain on silicon are shown
ISSN:1089-3539
2378-2250
DOI:10.1109/TEST.2005.1584022