A practical perspective on reducing ASIC NTFs

As chip, board and system technologies scale towards higher speeds and greater logic density, the effect of defects becomes more subtle, but more pervasive. As hardware designers push technologies to the limit, system DPM rates continue to increase, yet it becomes increasingly difficult to determine the nature of the failures. More and more often, components/ASICs which fail at board and system test are sent to suppliers, only to have them returned "NTF" (no trouble found). This paper presents some of the issues that Cisco Systems has experienced with respect to NTFs, and how some of those issues were resolved. These issues span from chip to system and from process to test to debug. The paper discusses the importance of a process to deal with NTFs and the importance of accurate data to determine and fix unwanted trends. Ultimately, most problems were resolved once the trend data and the offending logic were completely understood. Not all NTFs resulted from test escapes. It was clear, however, that some sort of "correlation" between the ASIC test and the system test needed to be in place to resolve/prevent NTF issues. In its conclusion, this paper advocates for much better correlation between the ASIC test on the component tester and the functional test in the system chassis