On-chip communication hardware resources for globally asynchronous and locally synchronous systems

Globally asynchronous and locally synchronous systems have been considered as a promising solution for the SOC to solve the problems of multiple clock distribution and multiple clock skew. The problem of regulated flow of data between the processing cores could be better addressed with local and global control mechanisms. In this paper an attempt to develop such interface architectures for point to point communication between processing cores is presented. The paper also provides a hierarchical control model for the local and global controllers.