Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage

Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage

In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition f...

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Bibliographische Detailangaben
1. Verfasser: Devanathan, V.R.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application specific integrated circuits
Circuit faults
Circuit testing
Controllability
Costs
Delay
Instruments
Lab-on-a-chip
Timing
Vectors
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Beschreibung
Zusammenfassung:In very deep submicron era, high transition fault coverage is crucial to ensure low levels of Defective Parts Per Million(DPPM). In this paper, the role of bi-partitioning a netlist for transition fault test is analyzed and novel bi-partitioned scan architectures are proposed to improve transition fault coverage with slow speed scan enable. Experiments on 5 industrial ASIC designs show a consistent increase in transition fault coverage.
ISSN:1081-7735
2377-5386
DOI:10.1109/ATS.2005.82