Device trends and implications on circuit design in advanced CMOS technologies

To conciliate scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization including dynamic body/well bias, gate dielectric scaling, mobility enhancement by strained-Si, SRAM process and design interactions, digital and analog device tradeoffs, and HV I/O considerations in advanced CMOS technologies.